With source-synchronous clocking, you still need to ensure that the clock is properly length matched so that the driver/receiver latches at the proper time.īi-directional bus in a schematic Use of Vias in PCB Bus Routing As digital systems have become more complex, standardized ICs have moved to a source-synchronous or embedded clock scheme. Suppressing jitter in the clock with a PLL is possible but not really practical, especially once we consider round-trip clocking on a bi-directional bus. Furthermore, each IC has some delay, and the clock lines from your common clock source need to be delay matched to account for the accumulated propagation delay. This is because each IC contributes some jitter on the signal traces, and jitter adds in quadrature. Using a common clock with a bus is more prone to mis-timed signalling as the number of driver/receiver ICs in series increases. Embedded clocks, where a clock signal is encoded in the first few bits of your bitstream, do not incur problems with clock routing in PCB bus routing. The same issue applies to routing a clock signal alongside your bus, whether it’s a common clock or source-synchronous clock. There is another important point to consider, which is trace length matching for parallel buses. Three important points in bus routing are designing for consistent trace impedance, proper termination, and a tight ground return path to minimize loop inductance. As some designers may question the wisdom of right angle turns in bus routing, I’ll address that point here as well. If you’re working on a new PCB design and you need to route a bus between different devices, there are some simple rules to follow to ensure your signals aren’t distorted and that successive devices are triggered correctly. The same goes for many digital systems that manipulate data in parallel. Modern computing simply wouldn’t be possible without PCB bus routing and layout.
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